This invention relates to the stacking of layers containing IC (integrated circuit) chips, thereby obtaining high density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. A unique aspect of this invention is that it stacks IC layers as TSOP's (thin small outline packages) in a footprint smaller than the TSOP footprint itself. Cost reduction is accomplished by relatively low cost forming of individual layers and the ability to incorporate off-the-shelf prepackaged and pre-tested IC's into stacks.
Another aspect of successful stacking of chip-containing layers is the ability of the BGA (ball grid array) interconnection to cheaply provide a large number of non-common (non-bussed) connections between individual layers themselves and the substrate to which the stack is attached.
The prior art contains several examples where a flexible circuit is used to interconnect unpackaged chips. Yamaji U.S. Pat. No. 5,394,303 shows a structure in which a flexible film with wiring layers is wrapped around a semiconductor chip, providing an increase in the number of terminals and a second surface for interconnections. McMahon U.S. Pat. No. 5,362,656 shows a structure in which a flexible circuit is used to route signals from interconnections with the top surface of the chip to ball connectors below the chip substrate. Paurus et al. U.S. Pat. No. 5,448,511 and Kimura U.S. Pat. No. 5,313,416 disclose schemes for creating a memory stack by interconnecting a series of memory devices or memory IC chips on a fan-folded flexible circuit board which carries the signals from the various IC chips to each other and out the bottom of the stack to the main PCB. Behelen et al. U.S. Pat. No. 5,598,033 shows a structure in which a flexible circuit is used to interconnect a semiconductor IC die to BGA contacts on another die displaced laterally, so that two stacks of dice can be interconnected in a zigzag manner.
What is not available in the prior art is a stack of IC chip-containing TSOP layers which are fully tested individually prior to stacking, can connect layers in the stack with each other and with the bottom surface of the stack using BGA's, and can provide custom interconnections including the separate connection of individual layer signals to the bottom of the stack. The current invention allows a large I/O count for mixed IC stacking or wide data paths, such as the assembly of wide word memory from layers of memory IC's having smaller word widths. Additionally, the current invention allows stacks having a smaller footprint than their constituent TSOP's, and allows them to be produced at low cost.